From 3D Integration to Optical interconnect: Building the Interconnect Foundation for the AI Era

Abstract

To sustain the current unprecedented growth of artificial intelligence (AI), the system architecture of the underlying compute systems used for training and inference will need to be fundamentally adapted. While transistor scaling continues to provide value, future system performance is increasingly constrained by data movement rather than computation. Bottlenecks are emerging at multiple levels of the hierarchy, including memory access, die-to-die communication, package interfaces, rack-scale connectivity, and data-center fabrics. As a result, interconnect scaling has become one of the most critical challenges facing the semiconductor industry.

Advances in 3D integration technologies, including hybrid bonding, wafer-to-wafer and die-to-wafer integration, chiplet architectures, and heterogeneous system integration, are enabling unprecedented increases in compute density, memory bandwidth, and functional integration while improving energy efficiency. These innovations are extending system scaling beyond the limits of traditional monolithic architectures and establishing the foundation for next-generation AI platforms.

As AI workloads continue to grow, however, electrical interconnects are approaching fundamental shoreline bandwidth density, reach, and power-efficiency limitations. Optical I/O is emerging as a key technology for overcoming these barriers, enabling high-bandwidth, low-latency, and energy-efficient communication across package, board, rack, and data-center scales. The convergence of advanced packaging, heterogeneous integration, silicon photonics, and optical interconnect technologies is creating new opportunities for scalable system architectures capable of supporting future AI infrastructure requirements.

Imec’s technology roadmaps and ongoing R&D demonstrate a progression from today’s co-packaged optics toward future wafer-level and 3D Optical I/O architectures, where photonic and electronic chiplets are tightly integrated using advanced assembly and hybrid bonding technologies. Combined with system-technology co-optimization across devices, packaging, photonics, and architecture, these approaches have the potential to deliver optical fabrics with multi-terabit per second per mm shoreline bandwidth densities and sub-pJ/bit energy efficiencies.

The convergence of 3D integration and Optical I/O represents a natural evolution of semiconductor system scaling, extending heterogeneous integration beyond electrical interconnects and providing the communication foundation required to sustain AI performance growth throughout the coming decade.

Biography

Imene Jadli is a physicist specializing in materials science and its applications, nanotechnology, and optoelectronics. She holds a Master’s degree (2015) and a PhD in Physics (2019) from the University of Monastir, Tunisia, where she conducted research in the Laboratory of Micro-Optoelectronics and Nanostructures.

After her PhD, she joined ASPITA, a private engineering school in Sousse, as Assistant Professor, teaching and managing university–industry partnerships while continuing her research at Monastir. In 2020, she moved to INSA Rennes, France, as Assistant Professor and researcher. Since 2022, Imene has been part of imec in Belgium, first in the 3D Integration team gaining expertise in advanced packaging, and now as Portfolio Manager in the Optical Interconnect team, driving innovation in photonic and interconnect technologies.