Logic Folding and Fine-Grained Logic-on-Logic 3D ICs: A Key Enabler of Tau Law

Abstract

Fine-grained 3D ICs distribute individual logic gates across multiple tiers using a logic-on-logic stacking architecture, enabling a level of integration beyond conventional memory-on-logic designs. This approach has demonstrated superior power, performance, and area (PPA) compared with coarse-grained 3D integration, and recent processors employing Logic Folding exemplify its growing adoption. Fine-pitch bonding technologies, such as face-to-face hybrid bonding, have made fine-grained 3D ICs practical. Realizing their full potential, however, requires advanced physical design methodologies that co-optimize millions of gates across tiers while efficiently managing millions of hybrid-bond interconnects. In this talk, we present novel algorithms and methodologies for physical design and multi-physics analysis of fine-grained 3D ICs, achieving significant PPA improvements over both coarse-grained 3D ICs and state-of-the-art 2D designs. We also discuss AI EDA techniques for reducing cross-tier connectivity while preserving PPA and improving yield, manufacturability, and testability.

Biography

Dr. Sung Kyu Lim is Dean’s Professor of Electrical and Computer Engineering at the University of Southern California, joining in Fall 2025 after over two decades at Georgia Tech. He received his B.S., M.S., and Ph.D. in Computer Science from UCLA. His research focuses on the architecture, design, and electronic design automation (EDA) of 2.5D and 3D integrated circuits, with over 450 publications. Dr. Lim is an IEEE Fellow and recipient of major awards including multiple Best Paper Awards (DAC 2023, TCAD 2022), and several Georgia Tech teaching honors. From 2022 to 2024, he served as a Program Manager at DARPA’s Microsystems Technology Office.