Heterogeneous Integration and Chiplet Architectures as the Next Scaling Paradigm

Abstract

As traditional device scaling becomes increasingly challenging, the semiconductor industry is entering a new era where system-level innovation drives performance advancement. Heterogeneous integration and chiplet-based architectures are emerging as key enablers of this transformation, allowing optimized technologies, functions, and process nodes to be combined within a single package to deliver unprecedented levels of performance, power efficiency, flexibility, and time-to-market.

This presentation will share Rapidus’ perspective on the future of semiconductor scaling, highlighting how advanced logic manufacturing and advanced packaging technologies must evolve together to create next-generation systems. Industry trends in heterogeneous integration, advanced packaging, and chiplet adoption will be discussed, along with the growing importance of co-optimization across front-end processes, interconnect technologies, packaging, and system architecture. The presentation will also examine the critical role of ecosystem collaboration in developing interoperable chiplet platforms and enabling a sustainable path for semiconductor innovation.

Biography

Rozalia Beica is Field CTO of Packaging Technologies at Rapidus Design Solutions, where she leads advanced packaging strategy, ecosystem partnerships, technology scouting and thought leadership. She has over 25 years of experience in advanced packaging, spanning materials, equipment, process integration, substrates, and system-level integration. Prior to Rapidus, she has held senior technical and executive roles at Semitool, Applied Materials, Lam Research, DuPont, AT&S, and Yole Développement, driving technology roadmaps, growth strategies, and commercialization activities. Her work has focused on 3D IC integration, wafer- and panel-level packaging, ultra-high-density interconnects, and advanced substrate technologies.

Rozalia has contributed to major industry roadmap activities, including the IEEE Heterogeneous Integration Roadmap (HIR), where she chairs the Wafer-Level Packaging Technical Working Group and a member of the technical substrate committee, and previously led 3D integration activities within ITRS. She also led the EMC3D consortium, an early initiative addressing TSV-based 3D integration challenges, bringing together industry and research partners to advance process integration and manufacturability.

Rozalia has been actively involved in industry leadership through IEEE EPS and IMAPS, including serving on the IEEE EPS Board of Governors and VP of Technology on the IMAPS Executive Council, and currently as Chair of the IMAPS Silicon Valley Chapter. She has led and organized major conferences such as ECTC, IMAPS Device Packaging Conference, Global Semiconductor Forum, SEMI Strategic Materials Conference, Build-Up Substrate Symposium, and IMAPS Executive Summit. She is the recipient of the inaugural IMAPS Leadership Award (2020) in recognition of her contributions to the industry, and R&D 100 award for her early development of lead-free SnAgCu electroplating processes for wafer bumping. She has authored multiple publications and delivered over 175 invited presentations. She also supports innovation through startup initiatives and serves on the Technical Advisory Boards of Terecircuits and Thintronics. She holds an Executive MBA and M.Sc. degrees in Chemical Engineering and Technology Management.