Exploring Test Flows and Test Access Architectures for Chiplet-Based Systems

Abstract

Chiplet-based systems are emerging as a key integration paradigm for combining heterogeneous dies within a single package. However, the transition from monolithic ICs to multi-die systems introduces new challenges in testing, yield management, and cost optimization. Since defects can arise during chiplet and interposer fabrication, as well as throughout multi-stage assembly and packaging processes, the final product is exposed to compound yield risks that make early defect screening increasingly important.

This talk explores test flows for 2.5D chiplet-based systems, including opportunities to introduce intermediate test stages beyond conventional wafer-level and final package testing. The trade-offs among test coverage, test cost, yield and total product cost are examined, highlighting the need for test-flow optimization. Case-study results illustrate the relationship between test coverages at different stages of the test flow and total product cost, demonstrating that coverage-, cost-, and yield-aware test-flow optimization is essential for identifying cost-effective test strategy. In addition, alternative package-level test access architectures are presented and compared with respect to scalability, interoperability, and package I/O efficiency. Overall, this talk provides insights into test strategies for chiplet-based systems, highlighting the trade-offs that must be considered to enable effective and cost-efficient testing.

Biography

Baris Arslan is a Principal Member of Technical Staff at imec in Leuven, Belgium, where he focuses on IC test and design-for-test (DfT) challenges, with an emphasis on chiplet-based systems. He received his M.S. and Ph.D. degrees in Computer Science from the University of California, San Diego. He held engineering positions at Intel, Marvell Semiconductor, and Qualcomm in the United States between 2005 and 2013, where he contributed to DfT strategy and structural test development for ARM and GPU cores, as well as advanced SoCs. He joined Istanbul Sehir University as an Assistant Professor of Computer Science in 2014. He later served as Data Science Director at OakNorth from 2017 to 2021 before joining Acibadem University in Istanbul as a faculty member, where he served as Deputy Head of the Computer Engineering Department. His research interests include DfT, adaptive test, test optimization and test access architectures.